
`include "defines.v"

module regfile(
	input  wire clk          ,
	input  wire reset        , 
	//READ PORT 1
	input  wire [ 4:0] raddr1,
	output wire [63:0] rdata1,
	//READ PORT 2
	input  wire [ 4:0] raddr2,
	output wire [63:0] rdata2,
	//WRITE PORT
	input  wire 	   we    ,
	input  wire [ 4:0] waddr ,
	input  wire [63:0] wdata ,

	output wire [63:0] regs_o[0: 31]      //difftest    
	);

reg [63:0] rf[31:0];  //64 Bit length, 32 Registers

// integer i = 0;
// initial begin
// 	for(i = 0; i<32; i = i + 1) begin
// 		rf[i] = 0;
// 	end
// end

//READ OUT 1
assign rdata1 = (raddr1==5'b0) ? 64'b0 : rf[raddr1];

//READ OUT 2
assign rdata2 = (raddr2==5'b0) ? 64'b0 : rf[raddr2];

//WRITE
always @(posedge clk) begin
	if(reset) begin
		rf[0    ] <= 64'h0;
		rf[1    ] <= 64'h0;
		rf[2    ] <= 64'h0;
		rf[3    ] <= 64'h0;
		rf[4    ] <= 64'h0;
		rf[5    ] <= 64'h0;
		rf[6    ] <= 64'h0;
		rf[7    ] <= 64'h0;
		rf[8    ] <= 64'h0;
		rf[9    ] <= 64'h0;
		rf[10   ] <= 64'h0;
		rf[11   ] <= 64'h0;
		rf[12   ] <= 64'h0;
		rf[13   ] <= 64'h0;
		rf[14   ] <= 64'h0;
		rf[15   ] <= 64'h0;
		rf[16   ] <= 64'h0;
		rf[17   ] <= 64'h0;
		rf[18   ] <= 64'h0;
		rf[19   ] <= 64'h0;
		rf[20   ] <= 64'h0;
		rf[21   ] <= 64'h0;
		rf[22   ] <= 64'h0;
		rf[23   ] <= 64'h0;
		rf[24   ] <= 64'h0;
		rf[25   ] <= 64'h0;
		rf[26   ] <= 64'h0;
		rf[27   ] <= 64'h0;
		rf[28   ] <= 64'h0;
		rf[29   ] <= 64'h0;
		rf[30   ] <= 64'h0;
		rf[31   ] <= 64'h0;
	end
	else  begin
		if(we && (waddr != 5'd0))
			rf[waddr] <= wdata;
	end
end

genvar j;
generate
	for(j = 0; j<32; j=j+1) begin
	  assign regs_o[j] = (we & waddr == j & j != 0) ? wdata : rf[j];
	end
	
endgenerate

endmodule
